GSoC’21: The Summer in Review

About the Project

BaseJump STL is to the hardware world as C++ STL is to the software world. It is a comprehensive hardware library for SystemVerilog that seeks to contain all the commonly used hardware primitives. FuseSoC is a package manager and set of build tools for reusable hardware building blocks facilitating the sharing of designs between projects and reusing open IP cores.

Objectives

  • Create core files for all BaseJump STL modules
  • Add lint targets for all cores
  • Port testbenches to work with verilator
  • Add verilator testbench targets for cores with testbenches
  • Create FuseSoC generator for generated cores like bsg_round_robin_arb

Progress Report

To see more details about my contributions you can check out my progress report below.

The Journey (and more about the project)

The first thing I did before starting the project was fully understanding the need for the project and state at that time of BaseJump STL and FuseSoC. I have summarized it as follows.

Why FuseSoC?

  • FuseSoC is non-intrusive: Most existing designs require no changes to work with FuseSoC
  • FuseSoC is modular: FuseSoC can be used to create an end-to-end flow
  • FuseSoC is extendable: Supports a wide variety of simulating and EDA tools and new EDA tools can also be added pretty easily
  • FuseSoC is standard-compliant: Much effort has gone into leveraging existing standards such as IP-XACT and vendor-specific core formats where applicable
  • FuseSoC is resourceful: FuseSoC already has a standard core library currently consisting of over 100 cores. Other core libraries exist, and more can be added to complement the standard library.
  • FuseSoC is free software: It puts no restrictions on the cores and can be used to manage your company’s internal proprietary core collections as well as public open-source projects
  • FuseSoC is battle-proven: It has been used to successfully build or simulate projects such as Nyuzi, Pulpino, VScale, various OpenRISC SoCs, picorv32, osvvm and more.

Why is it important?

How is this done?

FuseSoC makes use of cores. The FuseSoC package manager can discover cores stored locally or remotely and combine them into full hardware designs.

The Process

The porting process was actually quite straightforward. Each core module must have a core file with which FuseSoC can recognise it and reference it across different cores. So, the first step is creating core files for BaseJump STL modules. The next step in the process would be adding targets for the cores. Targets are workflows or simulators that you would like to push the core through. A simple first target would be a verilator lint-only and the next one would be a verilator testbench. Along with the targets, for the correct functioning of the modules, we need to have all the parameters of each core defined in the core file and set as required for each target or left empty if we want to pass the default value.

Core File

For those who are curious about the structure of a core file, I have added below the first core file I made which was for the bsg_dff module.

Verilator

Verilator is an open-source tool that converts Verilog code to its cycle-accurate behavioural model in C++ or SystemC. It does not simply convert the code, but it also compiles the code into much faster-optimized models, which are in turn wrapped inside C++ or SystemC modules.

Why Verilator?

Verilator models execute 10 times faster than standalone SystemC and 100 times faster than interpreted Verilog simulators like Icarus Verilog on a single thread. Multi-threading yields another 2–10x speedup.

Verilator testbenches

Verilator is very unforgiving in terms of non-synthesizable code blocks. To be able to use testbenches with verilator, they will have to be synthesizable. Commonly used shortcuts in Verilog testbenches such as manual delay elements cannot be present when working with verilator.

Generators

bsg_fakeram

bsg_fakeram generates black-boxed SRAMs that can be used in CAD flows when SRAM generators are absent or don’t exist. On giving a simple JSON configuration file containing technology node and SRAM sizing details as input, the generator will create the required block-box SRAM modules.

POC

To demonstrate the functioning of the project i.e., BaseJump STL integration into FuseSoC, a design has been created that makes use of BaseJump STL cores.

Empty Testbenches

Empty testbenches were added for all the cores so that testbench targets can be run now. These empty testbenches can later be modified into real testbenches as and when required.

Yosys

Yosys is a framework for Verilog RTL synthesis. It currently has extensive support for Verilog-2005 and limited support for SystemVerilog.

  • Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
  • Built-in formal methods for checking properties and equivalence
  • Mapping to ASIC standard cell libraries (in Liberty File Format)
  • Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
  • Foundation and/or front-end for custom flows

Objectives Completed

Proposed Objectives

  • Core files have been created for all the BaseJump STL modules
  • Lint targets have been added and tested
  • All existing and compatible testbenches were modified to work with verilator
  • Verilator testbenches have been added to the cores
  • FuseSoC generator created for bsg_round_robin_arb

Additional Objectives

  • Empty testbenches have been added for modules without testbenches (can be modified later as required to perform actual testing)
  • FuseSoC generator created for bsg_fakeram
  • ALU module created as a proof of concept of the project and tested successfully
  • Yosys targets have been added to all cores
  • Started work on porting Blackparrot to FuseSoC

The Project

The proposed project is completed. All the objectives that were a part of the proposal have been completed. Certain additional objectives had been undertaken along the course of the project to better the project, allow it to serve more users and create the foundation for future additions to this project. Many of these objectives have also been completed while some of them are in progress or yet to be done. I will continue working on this project in my free time and try to complete these objectives in a systematic manner.

Future Plans

  • Establish a CI\CD pipeline for BaseJump STL
  • Complete porting BlackParrot to FuseSoC
  • Add FuseSoC targets for industrial tools like VCS to the BaseJump STL cores.
  • Explore the possibility of adding open-source FPGA and ASIC flows

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H