Well, week 10 is up and the GSoC coding period has ended. I am both happy and sad to announce this. Happy that I was able to take up this project and complete what I set out to do. Sad that this program (and the summer) has ended.
The last week was spent testing most of the existing cores for possible flaws and adding yosys targets which could prove to be useful in future development. All the pending PRs on the cores repository have been tested, reviewed and merged. Work has also begun on porting
blackparrot to FuseSoC. The lint target has been made but is yet to be tested.
I have also started exploring means of producing code coverage measurement. Verilator has inbuilt features for code coverage measurements.
Well, this is the last weekly blog post. I will be doing a separate post summarizing my entire experience soon.
- Added yosys targets to all possible cores
- Test run all cores to verify they are functional
- Started work on porting
blackparrotcore to FuseSoC
- Complete code coverage measurements
- Establish a CI\CD pipeline for BaseJump STL
- Complete porting
- Add FuseSoC targets for industrial tools like VCS to the BaseJump STL cores.
- Explore the possibility of adding open-source FPGA and ASIC flows