GSoC’21 Week 2: Lint lint lint

Adithya Sunil
2 min readJun 22, 2021


Another week another story to tell.

“It’s been a long week.” — Me on Tuesday

Before going on to the weekly report, I will continue the project description from where I left off last. So, now we know what BaseJump and FuseSoC are, why they are important and what a core is. Now moving onto the actual process or methodology of creating these FuseSoC cores.

The Process

The porting process is actually quite straightforward. Each core module must have a core file with which FuseSoC can recognise it and reference it across different cores. So, the first step is creating core files for BaseJump STL modules. The next step in the process would be adding targets for the cores. Targets are workflows or simulators that you would like to push the core through. A simple first target would be a verilator lint-only and the next one would be a verilator testbench. Along with the targets, for the correct functioning of the modules, we need to have all the parameters of each core defined in the core file and set as required for each target or left empty if we want to pass the default value.

Core File

For those who are curious about the structure of a core file, I have added below the first core file I made which was for the bsg_dff module.

Want to know more about the project? You will have to wait for the next blog ;) (or check out the repo)

Week-2 updates

  • Modified core that refused to lint with verilator by adding warning ignore tags.
  • Created core files for 28 modules in bsg_mem with lint targets.
  • Ported 16 testbenches for bsg_misc modules to work with verilator.

Next week

  • Finish porting testbenches for bsg_misc modules and begin porting testbenches for bsg_mem modules.
  • Create core files for bsg_cache modules with lint targets.
  • Take a look at generators in FuseSoC and attempt to create one for round robin arbitration unit.



Adithya Sunil

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H