GSoC’21 Week 4: Testbenches

This week’s blog post is dedicated to a review of all the work done so far. Week 4 has ended and the project has progressed a lot since the beginning. Let me describe the timeline so far briefly.

I shall start with the community bonding period. During this period, I attended various meets with the mentors as well as the entire community. There were also discussions of the general do hows of the project and what I should perhaps do differently from what I had put forward in my proposal. We also came to a priority order for the modules to be ported first such that the more frequently used modules are ported first as they serve as dependencies for some of the later modules. So the community bonding period was effectively used to familiarise myself with the mentors as well the community members and make changes to the plan proposed initially to make it easier to proceed with the project and better suit the needs of the community.

The coding period marked the beginning of the actual project. There were a lot of hiccups in the first 1 week but after a few cores, things were a lot smoother. I was able to create core files for almost all the bsg_misc modules in the first week itself although some of them refused to lint as they weren't completely verilator compliant. These issues were overcome in the 2nd week by adding ignore warning tags to the verilator lint target. I was also able to complete creating core files for bsg_mem modules and begin porting the testbenches to work with verilator. The 3rd week also followed a similar pattern and I created lint targets for bsg_cache, bsg_dataflow and bsg_async. I was also able to finish porting the bsg_misc testbenches. The last week was also no less in terms of progress as I have created core files with lint targets for all bsg_noc, bsg_test, bsg_fsb and bsg_tag modules. The testbenches for bsg_mem cores have also been modified for verilator.

It is evident from this progress report that the last 1 month has been quite an enriching experience and I hope the coming month will be no less.

Week-4 updates

  • Created core files for all bsg_noc, bsg_test, bsg_fsb and bsg_tag modules with lint targets
  • Ported testbenches for bsg_mem cores to work with verilator

Next week

  • Complete creating FuseSoC generator for bsg_round_robin_arb
  • Port testbenches for bsg_dataflow and bsg_tag
  • Create core files for remaining modules




GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H

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Adithya Sunil

Adithya Sunil

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H

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