GSoC’21 Week 5: Generators

Adithya Sunil
3 min readJul 11, 2021


So what was this week all about, you ask. Well, generators.

Generators in FuseSoC are used to produce and specialize cores on demand. Core files contain a list of file sets with files written in SystemVerilog, C++, etc. These files are usually created to fulfil a general purpose in all use cases, but this is impossible in some instances. Certain applications require specialized files that are generated on demand based on certain parameters. This is where generators come into play.

Generators serve as a mechanism to generate core files on the fly during the FuseSoC build flow. There are 3 main components required for generating core files during the build flow:

  • Generator file: A generator file can be written in any language that is executable on the command line and accepts YAML configuration files as its first argument. Shown below is a generator file I have created to run a python script that generates a SystemVerilog file bsg_round_robin_arb.v and adds it to the core that calls this generator.
  • Generator core: These are core files that contain a section called generators that is used to notify FuseSoC that they contain a generator and describe how to use it. Each core can have multiple generators defined in it. FuseSoC will use the defined interpreter to run the command and pass the configuration file as the first argument. Shown below is a generator core written for the previously described bsg_round_robin_arb generator.
  • Core using the generator: The final step in the generator creation process is calling the generator from a core in which we wish to insert the generated file. This is done by adding a generate section to the core where the generator is registered and invoking the generator in the targets requiring it. Shown below is the core file bsg_round_robin_arb that requires the SystemVerilog file generated by the generator.

The generate section of the above core shows the generator being referenced and the value of the parameter channels being defined.

I hope this gives everyone a fair bit of understanding of FuseSoC generators and their usage.

Week-5 updates

  • Created FuseSoC generator for bsg_round_robin_arb
  • Ported testbenches for bsg_dataflow and bsg_noc

Next week

  • Test core files and testbenches to verify their functionality
  • Modify some of the core files according to recently merged PRs
  • Start working on hardened memory flow



Adithya Sunil

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H