GSoC’21 Week 6: Fakeram

bsg_fakeram generates black-boxed SRAMs that can be used in CAD flows when SRAM generators are absent or don’t exist. On giving a simple JSON configuration file containing technology node and SRAM sizing details as input, the generator will create the required block-box SRAM modules.

A sample configuration file is as follows

To use the BSG Black-box SRAM generator through fusesoc, we need to create a FuseSoC generator. I followed an approach similar to that of bsg_round_robin_arn from previous week. The FuseSoC generator is as follows

The generator core is as follows

Now to use this in a core, we can simply call it like any other FuseSoC generator. The only parameter required is the config file location which has to be defined for bsg_fakeram to work. An example core and config file are as follows

Running this core will generate the following black-box SRAM module

Week-6 updates

  • Created FuseSoC generator for bsg_fakeram
  • Started working on ALU design to demonstrate the process of creating new cores with BaseJump STL cores using FuseSoC

Next week

  • Complete implementation of ALU core
  • Integrate SRAM generated by bsg_fakeram generated into the ALU module




GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H

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Adithya Sunil

Adithya Sunil

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H

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