GSoC’21 Week 7: Proof of concept

To demonstrate the functioning of the project i.e., BaseJump STL integration into FuseSoC, a design has been created that makes use of BaseJump STL cores.

I have created a simple ALU that performs AND, XOR, NAND and ADD functions on its inputs. The block has 2 input signals A and B and a 2 -bit control signal which acts as the select line for selecting the operation to be performed on the inputs. The block has a single output signal which is the result of the selected operation.

The AND, XOR, NAND and ADD cores are available in BaseJump STL.

The SystemVerilog description for the design is as follows

A simple testbench can be written to test its functionality

The FuseSoC core file is as follows

The functionality of this core has been verified and it is working as expected. The next step in the process is to integrate a generator into this core. I have added the bsg_fakeram generator to this core and linked the ALU to the generated black-boxed SRAM. The SRAM module is added to the testbench and the pins are connected as required. The testbench is as follows

The new core file is as follows

The outputs of this core have also been verified manually and it is as expected.

This demonstrates a use case of the project. A lot of circuits can be constructed using the cores available in BaseJump STL and the integration of FuseSoC streamlines this process and allows users to define multiple flows for simulations or synthesis without having to manually handle the dependencies themselves as it is all taken care of by FuseSoC.

Week-7 updates

  • Completed implementation of ALU core
  • Integrated SRAM generated by bsg_fakeram generator into the ALU module

Next week

  • Complete making empty testbenches for all the cores
  • Update all core files to accommodate the latest changes
  • Test run all cores(lint) to verify the cores are functional

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Adithya Sunil

Adithya Sunil

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H