GSoC’21 Week 9: Yosys targets
This week was spent exploring yosys and the yosys tool support in fuseSoC. Yosys is a framework for Verilog RTL synthesis. IT currently has extensive support for Verilog-2005 and limited support for SystemVerilog.
Some of the features of yosys are as follows
- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows
FuseSoC has yosys support which makes it easy to synthesize through FuseSoC. Yosys is also used as a part of other flows like Symbiflow and Icestorm. Adding a Yosys target to BaseJump STL cores will allow for easier synthesis which would in turn help in FPGA development.
A yosys target can be defined as follows
arch parameter is used to tell yosys which series of FPGA’s we wish to synthesize for as yosys supports multiple vendors. The output format parameter is used to select the output format as json, edif or blif. The
-sv tag passed to yosys enables SystemVerilog support.
A small modification had to be made to the current BaseJumo macros in order to use the modules with yosys.
Yosys does not allow the use of bare default parameters and hence the marco is modified as follows
This will allow yosys to synthesize all the cores that contain only supported SystemVerilog features.
- Explored yosys and tried synthesizing simple smaller cores
- Added yosys targets to a few cores
BSG_INV_PARAMto work with yosys
- Add yosys targets to all possible cores
- Explore the possibility of adding icestorm and symbiflow targets
- Test run all cores to verify they are functional