GSoC’21 with FOSSi Foundation


How did I get here?

It didn't take much time for me to zone in on a single project and start working on the proposal. The mentors, Dan Petrisko and Prof. Michael B. Taylor, were very responsive right from the application phase and were happy to guide me through the process and provide feedback on my draft proposal.

Now speaking a bit more about my project.

About the project

The objective of my project is to port BaseJump STL to FuseSoC so that new projects can directly reuse these hand-optimized IP cores rather than starting from scratch. BaseJump STL has the hardware primitives defined in the form of SystemVerilog modules. FuseSoC makes use of core files that reference the provider, file sets and default targets allowing for the reuse of IP cores in the process of creating, building and simulating SoC solutions. FuseSoC allows for easier tracking and downloading of dependencies as well as versioning using VLNV tags making it much more convenient to work with large cores as well as keep track of changes to these cores. This project will involve porting all the modules as well as the testing infrastructure in BaseJump STL to work with FuseSoC.

The community bonding period of the program has come to an end and the coding phase has begun. I’m excited to be working on this project and I look forward to a very productive summer.

Stay tuned for more updates. You may connect with me on LinkedIn or take a look at my GitHub profile to know about my projects.



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Adithya Sunil

GSoC Student Developer @ FOSSi || Undergraduate Researcher @ CVEST, IIIT-H