Aug 16, 2021GSoC’21: The Summer in ReviewI'm Adithya Sunil and I have been working on porting BaseJump STL to FuseSoC under the GSoC’21 program at FOSSi. From the day the selected…Gsoc11 min readGsoc11 min read
Aug 16, 2021GSoC’21 Week 10: The End (or Just Another Beginning)Well, week 10 is up and the GSoC coding period has ended. I am both happy and sad to announce this. Happy that I was able to take up this…2 min read2 min read
Aug 8, 2021GSoC’21 Week 9: Yosys targetsThis week was spent exploring yosys and the yosys tool support in fuseSoC. Yosys is a framework for Verilog RTL synthesis. IT currently has…Gsoc2 min readGsoc2 min read
Aug 8, 2021GSoC’21 Week 8: Empty TestbenchesThis week was mostly spect consolidating the project’s current stage rather than improving it further. Empty testbenches were added for all…Gsoc1 min readGsoc1 min read
Jul 26, 2021GSoC’21 Week 7: Proof of conceptTo demonstrate the functioning of the project i.e., BaseJump STL integration into FuseSoC, a design has been created that makes use of…Gsoc2 min readGsoc2 min read
Jul 21, 2021GSoC’21 Week 6: Fakerambsg_fakeram generates black-boxed SRAMs that can be used in CAD flows when SRAM generators are absent or don’t exist. On giving a simple…Gsoc2 min readGsoc2 min read
Jul 11, 2021GSoC’21 Week 5: GeneratorsSo what was this week all about, you ask. Well, generators. Generators in FuseSoC are used to produce and specialize cores on demand.Gsoc3 min readGsoc3 min read
Jul 5, 2021GSoC’21 Week 4: TestbenchesThis week’s blog post is dedicated to a review of all the work done so far.Gsoc2 min readGsoc2 min read
Jun 27, 2021GSoC’21 Week 3: More CoresThis time I’ll talk a little bit about verilator and the testbenches.Gsoc2 min readGsoc2 min read
Jun 22, 2021GSoC’21 Week 2: Lint lint lintAnother week another story to tell.Gsoc2 min readGsoc2 min read
